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Descriptions
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10/30/08
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"Corrected" MCNC Netlists
The 22 largest MCNC netlists included in the VPR toolsuite have some odd
structures (LUTs with no inputs or no outputs, etc). These .blif netlists clean
up some of these oddities.
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10/30/08
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Heavily Pipelined Netlist
These circuits are pipelined/cslowed/retimed versions of the "corrected" MCNC
netlists. The X.pipe0.cslow1 blifs correspond to retimed versions of the
original benchmarks, with the number of registers going up from there.
One issue with these is while the basic connectivity of the LUTs is the same as
the unpipelined versions, the logic functions inside the LUTs are missing (only
the .names lines are present).
If you need the logic functions also (I only needed the basic circuit
structure), you'll need to write a script to match up the LUTs in these .blifs
with those in the "corrected" netlists to fill in the logic function line(s)
that normally follow each .names declaration.
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10/30/08
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Incremental Slack Placer
This code implement a simulated annealing placement tool with
incremental timing slack updates.
This code also contains the
Armada routing algorithm as an optional routing step.
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10/30/08
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Incremental Slack/Retiming Placer
This code implement a simulated annealing placement tool with optional
simultaneous simulated annealing-based retiming and re-packing.
This code is based upon the incremental slack placer, so refer to the documentation included in that
package for details on how to use this tool.
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